1. Field of the Invention
The present invention relates generally to the field of microelectronics. More particularly, the present invention is directed to an integrated circuit chip having a ringed wiring layer interposed between a contact layer and a wiring grid.
2. Background
A large portion of the semiconductor industry is presently devoted to the design and manufacture of application specific integrated circuit chips, or ASIC chips, that are used in many diverse applications, such as devices containing embedded systems. Examples of such devices include computers, cellular telephones, PDAs, thin clients, televisions, radios, domestic appliances, e.g., digital microwave ovens, dishwashers, clothes dryers and the like, automobiles, digital manufacturing, testing and diagnostic equipment and virtually any digital device for consumer or industrial use. Frequently, ASIC chips designed for different applications contain many of the same basic logic, memory and I/O elements, or cells, as one another. However, for different applications these cells may be present in different numbers, arranged differently and have different interconnectivity, among other differences. Examples of cells include RAM, I/O, adder, clock, latches and communication ports, among others.
Since many cell designs are often used repeatedly in creating new ASIC chips, manufacturers have built libraries of these cells. When designing a new ASIC chip, the manufacturer may then retrieve the necessary cells from the library and combine them with one another, and perhaps with custom-designed cells, in the manner needed for a particular application. Important purposes for creating libraries containing standard cells are to reduce the cost of designing and manufacturing ASIC chips, and to simplify the process of designing ASIC chips.
In a further effort to reduce costs and simplify the design process, manufacturers often complement their cell libraries by standardizing other features of ASIC chips. For example, manufacturers often standardize the type and arrangement of electrical contacts, i.e., power, ground and I/O contacts, for interfacing a completed chip with packaging and standardize the power and ground buses that provide, respectively, power and ground to the microelectronic devices, e.g., transistors, capacitors, diodes, among others, that make up the various cells.
Referring to the drawings, FIGS. 1, 1A, 2, and 3 show a presently used standardized arrangement of electrical contacts and power and ground buses in connection with an exemplary ASIC chip 10. Referring to FIG. 1A, ASIC chip 10 includes at its surface interposed arrays of I/O contacts 14, and power and ground contacts such as Vdd contacts 18, Vddx contacts 22, and ground contacts 26 (e.g., GND, Vref). These contacts may be solder bumps, such as controlled collapse chip connections (C4s) for flip-chip connectivity with a package (not shown). Electrical connectivity of power and ground contacts with a package may be alternatively effected using another technique, such as wire bonding. Such arrays of contacts 14, 18, 22, 26 generally allow ASIC designers to place the necessary cells 28, e.g., RAM cell, I/O cells, logic, and communication port cells, among others, wherever desired on chip 10 such that the cells are always relatively proximate the appropriate contact(s). In the arrangement shown in FIG. 1A, contacts 14, 18, 22, 26 are arranged in generally radial pattern, or pseudo-radial pattern, wherein the contacts in each of the four quadrants of chip 10 have mirror-symmetry along corresponding diagonals D—D, with lines of like contacts radiating outward from the diagonals toward the edge of the chip.
FIG. 2 shows an electrical structure 30 connecting Vdd contacts 18 with a semiconductor device layer 34 that contains the various semiconductor devices (not shown), e.g., transistors, capacitors, diodes, among others, that make up the various cells 28 (FIG. 1A) and other electrical components of chip 10. Electrical bus 30 comprises metal layers LM through (LM-n), interleaved with insulating layers I through (In). Those skilled in the art will understand that the number of metal layers and insulating layers will vary with the particular design and technology used to fabricate the chip. Metal layers LM through (LM-n) are illustrated only for Vdd contacts for clarity. Additional power supplies, such as ground and Vddx, would be connected to similar structures.
FIG. 3 shows conventional metal layers LM and (LM-1) as forming, in plan view, a rectangular bus grid 38 comprising orthogonal conductive strips or wires, 42 and 46, with the wires in each layer all extending in the same direction. That is, all of wires 42 in metal layer LM extend parallel to the X axis and all of wires 46 in metal layer (LM-1) extend parallel to the Y axis. In addition, wires 42 typically have the same widths and spacing as one another and wires 46 typically have the same widths and spacing as one another. For the power grid of chip 10, wires in each of layers LM and (LM-1) include Vdd wires 50, Vddx wires 54, and ground wires 58 interleaved with one another. As illustrated by FIGS. 2 and 3, at each location where like wires cross one another, e.g., one of Vdd wires 42 in metal layer LM crosses over one of Vdd wires 46 in metal layer (LM-1), the wires are electrically connected to one another with a corresponding via 60 extending through insulating layer (I1). Similarly, where a wire in metal layer LM passes beneath, or nearly so, a like contact, e.g., one of Vdd wires 42 in metal layer LM passes directly beneath one of Vdd contacts 18, a via 64, and perhaps also a horizontal strap (not shown), is provided to electrically connect that contact with that wire. As those skilled in the art will appreciate, metal layers beneath (LM-1) are similar to metal layers LM and (LM-1), but may contain progressively finer wires 68. Wires 72 of metal layer (LM-n) are closely spaced from one another so that each device in device layer 34 may be electrically connected thereto.
Area arrays of power and ground contacts 18, 22, 26 and uniform or nearly uniform power and ground grids in metal layers LM through (LM-n) permit designers to lay out the power and ground buses prior to arranging cells 28 (FIG. 1A) in device layer 34. Thus, the power and ground buses may be standardized, in large part eliminating the need to custom design these buses for each new ASIC design. However, problems can arise when electrically connecting power and ground contacts 18, 22, 26 to the corresponding wires 50, 54, 58 in metal layer LM, largely due to the fact that these wires run in only one direction, whereas the power and ground contacts are distributed in two dimensional pseudo-radial patterns. These problems include bussing discontinuities that lead to some regions of chip 10 having reduced ability to supply power to device layer 34 due to electromigration concerns and/or resistive voltage collapse (IR drops). In addition, neither metal layer LM nor metal layer LM-1 connect to a pseudo-radial pattern of contacts in a contact layer above with a regular grid of parallel wires below.